1. Field of the Invention
The present invention relates to a voltage level shifter circuit for shifting a voltage of an input signal to a high voltage or a negative voltage.
2. Description of the Related Art
Devices using a voltage different from a voltage of an input signal include a flash memory and an electrically erasable and programmable read only memory (EEPROM). In such devices, a voltage of an input signal must be shifted to a high voltage or a negative voltage. A circuit for conducting such shifting is referred to as a level shifter. Note that, in this specification, a high voltage refers to a voltage higher than that of an input signal. A voltage of an input signal is 3 V or 5 V, for example. A high voltage is 8 V, 10 V or 12 V, for example.
Japanese Laid-Open Publication No. 6-236694 discloses a high voltage level shifting circuit as shown in FIG. 14.
When a voltage at an input terminal T1 is Vcc, a transistor N1 is turned on, and a transistor N2 is turned off. In this case, transistors P2 and N1 are turned on. As a result, the voltage level shifter circuit outputs from its output terminal T2 a signal having a voltage Vpp through the transistor P2 as well as outputs from its output terminal T3 a signal having a voltage Vss through the transistor N1.
When a voltage at the input terminal T1 is Vss, the transistors N1 and P2 are turned off, whereas the transistors N2 and P1 are turned on. As a result, the voltage level shifter circuit outputs from the output terminal T2 a signal having a reference voltage Vss through the transistor N2 as well as outputs from the output terminal T3 a signal having a voltage Vpp through the transistor P1.
In this case, a voltage Vcc is 3 V, for example, a voltage Vss is 0 V, for example, and a high voltage Vpp is 10 V, for example.
Japanese Laid-Open Publication No. 58-125298 discloses a digital level shifter with low power consumption as shown in FIG. 15.
When a voltage at an input terminal T1 is Vcc, a voltage at a node nd5 is Vss, whereby a transistor P2 is turned on. In this case, a voltage at a node nd6 is Vcc, whereby a transistor P1 is turned off. As a result, the level shifter outputs a signal having a voltage Vpp from its output terminal T2 as well as outputs a signal having a voltage Vss from its output terminal T3.
When a voltage at the input terminal T1 is at Vss, a voltage at the node nd5 is Vcc, whereby the transistor P2 is turned off. In this case, a voltage at the node nd6 is Vss, whereby the transistor P1 is turned on. As a result, the level shifter outputs a signal having a voltage Vss from the output terminal T2 as well as outputs a signal having a voltage Vpp from the output terminal T3.
FIG. 16 shows a general negative-voltage shifter circuit.
When a voltage at an input terminal T1 is Vcc, a transistor P1 is turned off, whereas a transistor P2 is turned on. Therefore, a transistor N1 is turned on, and a transistor N2 is turned off. As a result, the negative-voltage shifter circuit outputs a signal having a voltage Vcc from its output terminal T2 as well as outputs a signal having a voltage Vn from its output terminal T3.
When a voltage at the input terminal T1 is Vss, the transistor P1 is turned on, and the transistor P2 is turned off. Therefore, the transistor N1 is turned off, and the transistor N2 is turned on. As a result, the negative-voltage shifter circuit outputs a signal having a voltage Vn from the output terminal T2 as well as outputs a signal having a voltage Vcc from the output terminal T3.
In this case, a voltage Vcc is 3 V, for example, a voltage Vss is 0 V, for example, and a negative voltage Vn is xe2x88x928 V, for example.
The voltage level shifter circuit as shown in FIG. 14 has the following problems when an input signal Si transtions from a voltage Vcc to a voltage Vss.
When the input signal Si having a voltage Vss is input, the transistor N1 is turned off. At this time, the transistor P1 is in an off state, and therefore a voltage at a node nd1 is kept at Vss Then, the transistor N2 is turned on. At this time, the transistor P2 is still in an on state, and therefore a through current flows through the transistors P2 and N2.
A parasitic load is produced between a terminal T5 to which a voltage Vss is applied and a node nd2. Accordingly, a voltage at a node nd4 is increased. When the voltage at the node nd4 rises to the value Vpp-Vthp1, the transistor P1 will not be turned on. Vthp1 herein refers to a threshold voltage for turning on the transistor P1.
As a result, the transistors P2 and N2 are kept in an on state, and a through current continues to flow through the transistors P2 and N2. Accordingly, the voltage level shifter circuit of FIG. 14 does not invert a voltage level.
The voltage level shifter circuit as shown in FIG. 15 has the following problems when an input signal Si transtions from a voltage Vcc to a voltage Vss.
When the input signal Si transtions from a voltage Vcc to a voltage Vss, a voltage at the node nd5 becomes Vcc. In this case, the transistor P1 is kept in an off state, and therefore a voltage at a node nd1 rises to the value Vcc-Vthn1. Vthn1 refers to a threshold voltage for turning on the transistor N1.
Then, a voltage at the node nd6 becomes Vss. Since the transistor P1 is in an off state, the voltage at the node nd1 is kept at the value Vcc-Vthn1. A voltage Vcc-Vthn1 is a voltage which is equal to or lower than a voltage Vpp-Vthp2. Vthp2 refers to a threshold voltage for turning on the transistor P2. Thus, the transistor P2 is still in an on state, and therefore a through current flows through the transistor P2, the transistor N2, and a part of an inverter INV3. Actually, a parasitic resistance is produced between a node nd2 and the terminal T2 which receives a reference voltage Vss, and therefore a voltage at a node nd4 rises. In the case where the voltage at the node nd4 is equal to or higher than the voltage Vpp-Vthp1, the transistor P1 is kept in an off state. Thus, the voltage at the node nd1 is kept at the value Vcc-Vthn1, and therefore the transistor P2 will not be turned off. As a result, a through current continues to flow through the transistor P2, the transistor N2, and a part of the inverter INV3. Accordingly, the voltage level shifter circuit as shown in FIG. 15 does not invert a voltage level.
The voltage level shifter circuit as shown in FIG. 16 has the following problems when an input signal Si transtions from a voltage Vcc to a reference voltage Vss.
When the voltage of the input signal transtions from a voltage Vss to a voltage Vcc, the transistor P1 is first turned off.
At this time, the transistor N1 is still in an on state, and a voltage at the node nd11 is slightly lower than the voltage Vcc. Therefore, the transistor N2 is kept in an on state. When the transistor P2 is turned on thereafter, a through current flows through the transistors P2 and N2. Accordingly, a voltage at a node nd15 falls to a value lower than the voltage Vcc.
It is now assumed that a voltage at a node nd12 falls to 1.5 V due to the influences of a parasitic load and the like. Then, a voltage at the back-gate of the transistor P2 drops, significantly degrading the current driving capability of the transistor P2.
Because of a significantly high channel resistance of the transistor P2, a voltage at a node nd14 falls to a value which is very close to a voltage Vn. It is noted that the voltage at the node nd14 is determined by a ratio of the channel resistance between the transistors P2 and N2.
In the case where the voltage at the node nd14 is lower than the value Vn+Vthn1, the transistor N1 will not be turned on. Vthn1 herein refers to a threshold voltage for turning on the transistor N1. Since a voltage at the node nd11 does not transition, the transistor N2 will be kept in an on state. As a result, a through current continues to flow through the transistors P2 and N2. Accordingly, the voltage level shifter circuit of FIG. 16 does not invert a voltage level.
A voltage level shifter circuit according to one aspect of the present invention includes a first transistor having a source, a drain, and backgate and gate; a second transistor having a source, a drain, and backgate and gate; and a switching section for receiving an input signal and changing respective voltages to be applied to first and second nodes, wherein one of the source and the drain of each of the first and second transistors is connected to a third node, the backgate of each of the first and second transistors is connected to the third node, the other of the source and the drain of the first transistor and the gate of the second transistor are connected to the first node, and the other of the source and the drain of the second transistor and the gate of the first transistor are connected to the second node, the voltage level shifter circuit further including a resistance equivalent element having first and second ends, a high voltage being applied to the first end, and the second end being connected to the third node.
In one embodiment, the resistance equivalent element is a resistor.
In one embodiment, the resistance equivalent element has at least one p-channel MOS transistor.
In one embodiment, the resistance equivalent element has first and second p-channel MOS transistors, and a channel width of the first p-channel MOS transistor is larger than a channel width of the second p-channel MOS transistor.
A voltage level shifter circuit according to another aspect of the present invention includes a first transistor having a source, a drain, and backgate and gate; a second transistor having a source, a drain, and backgate gate; and a switching section for receiving an input signal and changing respective voltages to be applied to first and second nodes, wherein one of the source and the drain of each of the first and second transistors is connected to a third node, the backgate of each of the first and second transistors is connected to the third node, the other of the source and the drain of the first transistor and the gate of the second transistor are connected to the first node, and the other of the source and the drain of the second transistor and the gate of the first transistor are connected to the second node, the voltage level shifter circuit further including a resistance equivalent element having first and second ends, a negative voltage being applied to the first end, and the second end being connected to the third node.
In one embodiment, the resistance equivalent element is a resistor.
In one embodiment, the resistance equivalent element has at least one n-channel MOS transistor.
In one embodiment, the resistance equivalent element has first and second n-channel MOS transistors, and a channel width of the first n-channel MOS transistor is larger than a channel width of the second n-channel MOS transistor.
A voltage level shifter circuit according to still another aspect of the present invention includes a first transistor having a source, a drain, and backgate and gate; a second transistor having a source, a drain, and backgate gate; a third transistor having a source, a drain, and backgate and gate; a fourth transistor having a source, a drain, and backgate gate; and a first switching section for receiving an input signal and changing respective voltages to be applied to first and second nodes, wherein one of the source and the drain of each of the first and second transistors is connected to a third node, the backgate of each of the first and second transistors is connected to the third node, the other of the source and the drain of the first transistor and the gate of the second transistor are connected to the first node, the other of the source and the drain of the second transistor and the gate of the first transistor are connected to the second node, one of the source and the drain of each of the third and fourth transistors is connected to a fourth node, the backgate of each of the third and fourth transistors is connected to the fourth node, the other of the source and the drain of the third transistor and the gate of the fourth transistor are connected to a fifth node, and the other of the source and the drain of the fourth transistor and the gate of the third transistor are connected to a sixth node, the voltage level shifter circuit further including a second switching section for changing respective voltages to be applied to the fifth and sixth nodes based on respective voltages at the first and second nodes; a first resistance equivalent element having first and second ends, a voltage being applied to the first end, and the second end being connected to the third node; and a second resistance equivalent element having first and second ends, a negative voltage being applied to the first end of the second resistance equivalent element, and the second end of the second resistance equivalent element being connected to the fourth node.
In one embodiment, the first and second resistance equivalent elements are resistors.
In one embodiment, the first resistance equivalent element has at least one p-channel MOS transistor and the second resistance equivalent element has at least one n-channel MOS transistor.
In one embodiment, the first resistance equivalent element has first and second p-channel MOS transistors, a channel width of the first p-channel MOS transistor being larger than a channel width of the second p-channel MOS transistor, and the second resistance equivalent element has first and second n-channel MOS transistors, a channel width of the first n-channel MOS transistor being larger than a channel width of the second p-channel MOS transistor.
Thus, the invention described herein makes possible the advantage of providing a voltage level shifter circuit capable of stably inverting a voltage level upon transition of a voltage level of an input signal.
This and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.